the measurement you are talking about is something I call "Latency"..
The way I would do this is to create model of the Sigma Delta ADC that has 0 latency, then add a number of registers on the output to hold the prior values up to (and including) the maximum possible latency of your SD-ADC..
Also provide a control bus on your model to allow selection of the various holding registers for your output..
- for a one time -visual- test compare the output of each of the registers to the output of the real ADC..
for a more automated test.. separate the registers from the Reference ADC model.. and write (as a verilog model) a model that will have the registers and comparsion blocks that will (on each clock edge) tell you which delayed output matches the SD-ADC under test.
- to go further,
consider finding the closest match to 2-4 samples, perhaps ignoring minor differences as small as 1-2 LSB's
------------
In an analog sense, you could turn the "under test" and "reference"(+ delayed) outputs back to analog levels and then take the difference between the test output and each delayed on.. Integrate these and the one closest to Zero after a representive sample set would give you the number of cycles of latency..

hope this helps,
Jonathan

ic_engr,

  Isn't each of the integrator a effectively a delay
element? So in a second-order ADC there are two
delays elements or a latency of two clock cycles.
However, I don't think that the delay in the modulator
is relevant. It is the delay in the digital filter that
determines the latency of the ADC. Since the output of
the modulator is effectively noise, does it matter how
much latency there is from the input to the modulator
output? If you define latency in terms of data in to
data out, then you need to include the digital filtering
in the latency calculation.

                                                         Best Regards,

                                                           Sheldon