I think that one very useful feature could be a stress chart of a layout, given the kind of package used (plastic/ceramic). I am not certain if it would be extremely relevant, but atleast we should start to view our analog layouts the way they are - 3-dimensional.
Currently, the layout looks like a tangled net with lines of different colors running all over it. But, in reality, it is layer on top of layer, and with the existing computing capabilities, it should be very easy to provide a stress chart, allowing the user to also zoom in into an area and look at a 3-D view of the stress map or see if his gate poly is suffering significant stress or shear action.
This should help in deciding the effectiveness of a floorplan or dummy devices. After all, the on-chip stresses are not really random and can be predicted quite accurately, given the requisite information.
Of course, high levels of matching are specially desirable in precision bandgap circuits, while in the rest, one just tries to make a robust device. So this may just be a niche application.