I've been simulating a 12-bit current-steering DAC, initially with ideal current sources, switches etc. I've been introducing non-idealities into the current sources (6 binary-weighted sources, 6 thermometer-decoded bits) and looking at the effects on INL, DNL, SFDR, SNR etc. So far, so good.

Now I've moved on to using a couple of technology design kits and replaced the ideal components with transistor level schematics and their corresponding models. Simulations on my DAC now always show a strong peak at 3f that decreases the SFDR drastically. If I replace the current sources with ideal models the spur disappears. I've tried introducing various types of artificial mismatch into the ideal sources (up to 0.5 LSB) but all that does is raise the noise floor, not produce a sharp peak.

Any ideas where this 3f peak is coming from?

Thanks Sheldon - I've just managed to replicate the 3f spur by using ideal sources in parallel with a resistance, to simulate the output impedance.