The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
May 5th, 2024, 1:20am
Pages: 1
Send Topic Print
Assura Extraction problem in IBM 7RF (Read 3253 times)
vipul
New Member
*
Offline



Posts: 3

Assura Extraction problem in IBM 7RF
Oct 11th, 2005, 2:56am
 
Hi,

I am using the IBM 7RF kit to design circuits for frequencies above 10GHz. The parasitic extraction using Assura seems to be inaccurate for parasitic resistances. Sometimes, it shows resistances as big as several kil-ohms, while Diva shows only a few ohms.
Has anyone had a similar problem? Is it a bug?
I am using IC5141 and Assura 314 on a Linux machine.
Is Diva reliable? (e.g how much deviation can I expect in measurements)
I can provide more details of what procedure I am following exacly, if that helps.

Thanks
Vipul
Back to top
 
 
View Profile   IP Logged
Andrew Beckett
Senior Fellow
******
Offline

Life, don't talk to
me about Life...

Posts: 1742
Bracknell, UK
Re: Assura Extraction problem in IBM 7RF
Reply #1 - Oct 12th, 2005, 1:45pm
 
Note that Assura tends to lump together resistors far more than Diva does - Diva often leaves lots of small resistors in a complex mesh, because it does only limited reduction (and even then, it will only reduce if it can make the network smaller with the same overall resistance, and it will only combine resistors which came from the same layer - if my memory is correct).

So you may not be comparing like with like?

Any concerns you have over accuracy of the extraction rules should go to IBM, I'd have thought.

Regards,

Andrew.
Back to top
 
 
View Profile WWW   IP Logged
vipul
New Member
*
Offline



Posts: 3

Re: Assura Extraction problem in IBM 7RF
Reply #2 - Oct 14th, 2005, 12:57am
 
I found the answer on the Cadence Sourcelink website. Assura does some Wye to Dlta transformations on the resistive network that it extracts, and in turn comes up with large values. This does not affect the electrical equivalence of the extracted view; just that what it back-annotates on the schematic gives the user a wrong impression. A work-around is to specify a larger value for the minR parameter.
I have some more problems that I am writing in a separate post.

Thanks for your help
Vipul
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.