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AHB Slave.. (Read 2797 times)
hardik
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AHB Slave..
Oct 14th, 2005, 1:42am
 
hi,

i m designing an AHB slave..can u tell me how can i use HINDEX to select the correct SLAVE select signal for me??

thank u,
hardik
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jbdavid
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Re: AHB Slave..
Reply #1 - Oct 17th, 2005, 1:06am
 
Hi,
Not knowing what AHB you are referring to.. a quick websearch found a couple of references to Eureka Technologies, and the Advanced High-performance Bus..
and I think you are asking a question about the Bus interface itself, rather than about modeling its behavior.
- Please understand that HERE, AHDL is for ANALOG HDL, which describes a blocks ELECTRICAL characteristics, and very few of use are even aware that ALTERA has a proprietary Digital HDL they also call AHDL (I think its kept around for backward compatibility ??)
Just to be clear.. I am NOT aware of any HINDEX feature in Verilog-A, Verilog, or Verilog-AMS, so I am at a loss for giving you further help..
jbd
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jbdavid
Mixed Signal Design Verification
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