Hello:

    I'm trying to do a LNA design project myself. I'm using a regular
2 stage common source nmos transistor. the 1st stage is a cascode.
the bottom nmos has a source degeneration inductor to provide 50 ohm,
there is a inductor connected to  its gate to resonate out the Cgs at
desired frequency. it's 5.6GHZ in my case. the top nmos has a drain
inductor. the 2nd stage is only 1 common source nmos. it  doesn't
have source degeneration inductor. it does have a inductor at drain. I
built it and started to run transient analysis using spectre. I have
some questions and hoping someone may help me out.  Vdd is 1.4v
0.13um process.

1)in 1st stage, on waveform I noticed the voltage of node between
source degeneration inductor and nmos source is almost 0 volts, with
very small fluctuation. is it supposed to be this way? based on classical
theory, the series RLC circuit at resonence the voltage across inductor
and cap) is high. of course my inductor only is 0.25nH.

2)the voltage of the node between drain of top nmos and the
inductor goes up and down. it can go above Vdd voltage. I think it's due
to the inductor. is this correct?

  I guess I don't know what should these node behave for a properly
designed LNA. how do I know I picked the right values for all the
inductors and capcitors and nmos size? i used equations in Tom Lee's
book. I used minimum device length.  then calculated width.  
  of course I haven't started s parameters measurement. I just trying to
make sure my LNA is working first before I try to improve the performance.
  thanks a lot for any hint.

hang

 thanks Sheldon for your reponse.
 I have more questions regarding the LNA design.  
because the 1st stage output voltage can go above
power supply, it will be difficult to set the 2nd stage
in saturation mode, since the output node of 1st stage
is connected to the gate of 2nd stage, through a
capacitor. the source of this nmos is connected to
ground. from my simulation I see the 1st stage output
voltage basically bounce around VDD. as a result 2nd
stage nmos is in linear region all the time. it doesn't
have much gain while burning a lot of power, i.e. it
draws a lot of current. if I increase drain inductor of 2nd
stage, then its drain node voltage (output node) may  
go higher than gate. this could put it in saturation
for some time till the drain voltage goes lower. it starts
to have some gain. but then spectre warns it goes
above oxide break down voltage.
     I don't know what to do now. do people use 2
stage LNA in real circuit? if yes, how do they set 2nd
stage in saturation mode?
      many thanks.


Hang


   

      thanks uncle_ezra for your response.
      I checked my design. there is something wrong
with the bias at 2nd stage. I corrected it. now the
waveform makes sense.
      I'm doing a 2 stage LNA design, for more gain I
guess. actually I downloaded the project from a
university's RF course web site. they specified 2 stage
LNA.
      Now I understand the DC blocking cap much
better. I always know cap can pass high frequency
signal, block DC signal. but only limited to at high freq.
its impedance is small, at DC impedance is infinite. I
couldn't visulize how this property is used in RF. so I
post it here hoping it may help someone who has the
same issue  as me.
     the purpose of DC blocking cap is it shifts input
signal level to the bias point. for example, a sinewave
of 0.9V-1.1V means the DC level is 1 V, then add AC
variation of 0.1V to it. if this signal is connected to a
cap, but at the other side of  cap is 0.5V bias, then
only AC portions pass through the cap and added to
bias. so final signal is 0.4V-0.6V. this is very
useful because we can not predict input signal level.