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N-Well Shielding (Read 3321 times)

uncle_ezra

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N-Well Shielding
Nov 24^th, 2005, 3:40am

In a p-type substrate, the n-well can be placed under capacitors, inductors and resistors to provide a low-capacitance shield. My question is whether you can leave the n-well terminal floating? In simulation it seems to be ok but not sure if there will be any side effects after fabrication.

I know ideally you want to connect to a clean Vdd but since I don't have that available is it ok to leave the terminal floating?

Thanks

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uncle_ezra Community Member Offline Posts: 90	Re: N-Well Shielding Reply #1 - Nov 28^th, 2005, 1:18am So I was told it is ok to leave the terminal floating.
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hrkhari Junior Member Offline Posts: 21	Re: N-Well Shielding Reply #2 - Dec 18^th, 2005, 5:50pm I believe that the n-well shielding should be connected to Vdd to further avoid accumulation of stray charges if it is left floating. Rgds
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Paul

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Switzerland

Re: N-Well Shielding
Reply #3 - Dec 19^th, 2005, 1:13pm

Hi,

I have seen both and if your foundry does not explicitly forbid this practice (DRC rules), it should be OK to leave it floating. Don't forget however that the result is not the same. In one case your inductor/resistor sees a fixed parasitic capacitor to a clean Vdd, in the other case (floating) it sees a capacitive divider to the possibly noisy substrate. The latter is usually better for speed, but not always for parasitic coupling.

Paul

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