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Help on Pipeline ADC design
Nov 27^th, 2005, 10:02pm

Hello all,
I am just beginning to design pipeline ADC 3 months ago and have many questions.:)

The ADC I am working with is 50MSPs in 0.18um, 12 bit SNDR, 14bit SFDR(Are these specs realistic?). The OTA is telescopic two-stage amplifier. Gain =80dB, settling time around 9n (dynamic settling within 14 bit level).

After I complete the first stage of MDAC, I measured the residue of this MDAC *( because simulating whole pipeline ADC will take forever). To see the non-linearity, I constructed an ideal MDAC output. Then I took the difference of these two outputs. If the simulated output does not have any non-linearity, then the difference should be a flat curve . However, for my case, the difference at the transition (the threshold of comparator) has some discontinuity. After I modified the cap a little bit ( i.e, change the feedback gain), the discontinuity can be corrected. However, the step between first point and the second point after the transition is much larger than it should be. It shows as a big spike on the curve of the difference. The input I tried is down ramp and up ramp signal. This spike showed up after every transition.

Do you have any idea on where this spike coming from? Any feedback will be highly appreciated! I have struggled for this about 3 weeks .

Thanks, rain

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Sid

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Re: Help on Pipeline ADC design
Reply #1 - Nov 28^th, 2005, 7:55pm

Hello Rain,

I am not sure I understand everything you say, but I will give you a few pointters.

14 bit SFDR, I believe, means you are trying to get 14-bit linearity (INL). Hence, you probably lower your quantization noise by quite a lot and allow more budget for thermal noise. This is a good idea and may actually help save power when you target your 12-bit SNDR. You do not mention a power budget, but if you have one, that could limit your ability to meet your specs. A gain of 80 dB may be too low for 14-bit linearity...you probably need at least 100 dB to ensure things don't become too non-linear with temperature drifts. Also, you must consider calibrating for capacitor mismatch at 14-bits.

I like to simulate my gain-of-2 (or 2^n) S/H separately and do a FFT of the held output in SPICE to ensure it meets all distortion specifications at your 50 MSPS (i.e. SFDR). Remember to either use SpectreRF or do an FFT only for the final "held" value (you should not consider the transient spikes before the output settles).

For noise you can either use SpectreRF or conventional .noise analysis in SPICE (this only works if a bias point is avaiable and hence you will have to make some hacks in your switched cap system). There is a very helpful document on noise simulations in Switched-Cap systems in SpectreRF on designers-guide.org.

Hope this helps.

-Sid

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vivkr

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Re: Help on Pipeline ADC design
Reply #2 - Nov 28^th, 2005, 11:50pm

Hi Rain,

If I understand you correctly, you have modified your feedback factor by changing the cap ratio a little bit. This is the same as introducing some capacitor mismatch into your MDAC.

When you do this, the height of the transition step(s) at each comparator trip point will change. You can write a few simple equations by hand to see this.

If you want to use this new cap ratio for your real MDAC, then you should also use the same ratio to calculate the ideal MDAC output values. Then you will not see a large discontinuity in the error that you measure.

If you already are doing this, then perhaps the problem lies elsewhere.

Regarding the feasibility of your design, it is certainly within the state-of-art. I agree with Sid that the power consumption you are allowed will decide the ease of realizability. Also, that you probably need more DC gain (settling accuracy) than 80 dB and some form of calibration.

Regards
Vivek

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forest_rain

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Re: Help on Pipeline ADC design
Reply #3 - Nov 29^th, 2005, 8:33am

Hello Sid and Vivek,

Thank you very much for spending so much time to explain that to me ! I think I did not prescribe my project clearly.

I am targeting at 12 bit INL, 12bit SNDR, and 14bit SFDR. I am going to use a digital calibration, which can calibrate the static error but cannot handle the dynamic error. Therefore, I am trying to push the dynamic performance as much as possible.

(If I do not use calibration, then SFDR is limited by INL, am I right? )

VDD is 1.8V, the output swing is 2Vpp, Vref=1V, gain is 4 (One cap is 1.5 pF, and the other is 0.5 pF) . The PM is around 65, and the frequency of closed-loop OTA at gain of 4 is around 200MHz, so the GB around 800MHz. The current of the first stage is 0.5mA and for the second stage, it is 3mA.

The residue vs. the input is 2.5bit/stage architecture, so it has six transitions at +/-0.625, +/-0.375,+/-0.125.

I do not have S/H. The input signal is applied to the MDAC directly. During phase one, the input are charging the sampling capacitors, the differential output of the OTA are shorted with a transmission gate (should I use two switches to short two output terminals to common mode voltage?) and at the same time the comparator are making decisions. During phase two, one of the caps is flipped and connected to the output. One plate of the other cap is connected to a reference voltage (a DAC output).

I applied a ramp signal to one stage MDAC, and measured the output (the residue). After I compared the output with the ideal MDAC output values (assume gain is 4), I see large discontinuity. Then I went back to adjust the capacitor ratio( the nominal ratio is larger than 4, I think this may be caused by finite gain of OTA), and then compared to the ideal MDAC output values, the large discontinuity then disappeared, just like Vivek suggested. However, there is still 6 spikes around six transitions points. For example, if the ramp sweep through -0.625V. Before it reaches-0.625V, the output is closed to 0.5, after it pass -0.625, the first point should be -0.5, and the second point should be one LSB larger. After I corrected the gain, if compared to the ideal MDAC output values, the differences at these three positions should be the same (if offset exists). However, the reality is the 1st and the 3rd have similar differences but the difference at 2nd points is about one LSB larger or smaller than 1st and 3rd depending on up or down ramp. I guess this is caused by previous error dependence (may be insufficient settling?), but I could not figure out where it comes from.

As Sid said, I only did FFT (using matlab after export the data) to the �settled value� (here I took the output value of the MDAC at the end of Phase 2 clock). And I found out that the SFDR is only around 82 dB. Even after I changed to ideal OTA( VCVS), it is still about the same. I am not sure this is limited by the bootstrapped switches (which only have 90dB at very low frequency) or because I have bad static INL performance.
I hope I made it clear so that you can help me without wasting too much time.

Thanks again, Rain

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vivkr

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Re: Help on Pipeline ADC design
Reply #4 - Dec 1^st, 2005, 11:40pm

Hi Rain,

Your problem seems to be a bit puzzling. I assume that you have not used any mismatched elements, and that all voltage sources etc. are ideal etc.

Just a few suggestions that might help trace the source of the problem:

(1) Replace the comparators you use with ideal ones, and see if the problem you are seeing is owing to comparator hysteresis.

(2) Although it is not possible to simulate the entire ADC in a reasonable amount of time, you can synthesize the ideal output of the stages following this one in MATLAB or using a simple C script, as you have the residues available. This can show you if the problem is really severe enough for your
overall ADC performance.

(3) I think you had the same problem even with an ideal OTA. Did you try to increase the gain of this OTA by say a factor of 10 and see what happens?

(4) Finally a note about your use of the MDAC without a sample-and-hold. Although you can use this arrangement, it would be good to ensure that you have sufficient SFDR from the output of the S&H. The 2 switches that really matter most are the sampling switches, and for high frequencies, even the bottom-plate sampling technique (opening the lower switch first) does not guarantee signal-independent charge-injection. Try one run with ideal switches, or an ideal S&H.

(5) Last but not least, I understand that you are using a ramp input. What is not clear to me is whether this ramp is a fast one, or a slow one. Your real and ideal circuits may be different in terms of the input they sample. Alternatively, there may be too few points in the ramp for you to accurately measure the INL in the way that you are doing it now. Try increasing the number of points on the ramp by slowing it down (assuming it is a transient ramp).

Perhaps, one of these steps will give you the source of the problem. It would be good to know where it comes from.

Regards
Vivek

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forest_rain New Member Offline Posts: 3	Re: Help on Pipeline ADC design Reply #5 - Dec 2^nd, 2005, 9:29am Hello Vivek, by any chance you know my friend Vipul Katyal
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vivkr Community Fellow Offline Posts: 780	Re: Help on Pipeline ADC design Reply #6 - Dec 11^th, 2005, 11:34pm Hi Rain, Yes, I do, but could you find the source of your mysterious problem ? Regards Vivek
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