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epitaxial layer (Read 5597 times)
sugar
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epitaxial layer
Dec 19th, 2005, 3:16am
 

anybody who knows the purpose of epitaxial layer?
Why not make transisters in p-sub directly?
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kwkam
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Re: epitaxial layer
Reply #1 - Dec 19th, 2005, 5:40am
 
Epi layer is often used in the bipolar process. Usually, it make a N or P buried layer on the surface of P-sub. Then a layer of monolithic Si grow on the top of Buried layer for further step. For more detail, you can read some semiconductor process book.
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Paul
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Re: epitaxial layer
Reply #2 - Dec 19th, 2005, 1:20pm
 
Epi substrates usually have lower resistivity compared to plain processes. For some reason, it is frequently used in bipolar and BiCMOS processes, I believe.

Due to the lower resistivity, it minimizes the risk of latch-up. It seems to me it used to be very popular during a couple of process generations for digital circuit design (maybe somebody else can confirm this?). It is however terrible in terms of substrate noise, because the noise almost propagates everywhere.

Paul
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sugar
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Re: epitaxial layer
Reply #3 - Dec 20th, 2005, 3:28am
 
why process guys don't integrate transistors in the heavily doped p-sub layer? what's the limitation?
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Geoffrey_Coram
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Re: epitaxial layer
Reply #4 - Dec 22nd, 2005, 9:17am
 
Wouldn't the collectors of all the PNPs be shorted together, if the PNPs were made in the p-sub layer?
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If at first you do succeed, STOP, raise your standards, and stop wasting your time.
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sugar
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Re: epitaxial layer
Reply #5 - Dec 22nd, 2005, 4:44pm
 
here I am talking about cmos process, not bipolar.
anybody knows the reason?
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sheldon
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Re: epitaxial layer
Reply #6 - Dec 22nd, 2005, 5:50pm
 
River,

  Epitaxial  layers are used because they are more lightly
doped than the layers below them.  Growing an epitiaxial
layer is the only method to create a more lightly doped
layer on top of a more highly doped layer. For bipolars, an
n-epitaxial is used. This layer allows npn transistors to
have an N+ buried subcollector. The buried subcollector
suppresses the beta of the vertical pnp inherent in the
npn structure. For CMOS transistors, a p+ wafer is used
with a p-epitaxial layer to suprress the beta of the
parasitic bipolar that causes latch-up.

  Lower doped regions are preferred because the
breakdown voltage is higher, the junction capacitances
are lower, device output resistances are higher, device
threshold voltages are higher, ... This is a fundamental
challenge for our industry. Think about what happens as
processes are scaled down from 0.35um --> 90nm. The  
doping concentration of the substrate increases meaning
that the transistors have lower breakdown voltage,
less output resistance, ...

 The p+ substrates are doped near to degeneracy,
that is, they are more like "conductors" then
"semiconductors". You can not build devices in transistors
in a p+ substrate.

  Lateral pnp devices are built in n-epitaxial bipolar
processes so the devices are isolated. In CMOS
processes it is more typical to build vertical pnp
transistors using n-well as a base. These device
do not have an isolated collectors.  

                                             Best Regards,

                                                 Sheldon


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Re: epitaxial layer
Reply #7 - Dec 26th, 2005, 7:34am
 
Sheldon

thank you very much.   Tongue

River
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