Paul wrote on Mar 8th, 2006, 12:14pm:Hi Alan and Marc,
Very interesting thread indeed. I wasn't aware of this problem as the process I am currently using is purely digital and doesn't offer MiM caps. I use vertical fringing caps which do not exactly deliver the same density compared to MIM, but are quite linear too (and become better with each process generation :)).
I wonder whether you would expect any leakage issues due to the tie-down diodes in switched-cap circuits, which would be a typical application for MiM caps? Of course the wiring Alan describes in the last post is a good work-around, if accepted by the foundry (and supported by the DRC deck...).
Thanks for sharing your experience.
Paul
I actually just used MiM caps in a 90-nm process and they didn't require tiedowns.
I would imagine that the tiedowns are eventually going to drain the charge from any capacitive node. In quasi-floating gate circuits there is a reverse diode to make the high impedance connection and it definitely drains charge.