the following circuit is used as 5V tolerance input circuit for a 3.3V CMOS process.
all the MOSs are 3.3V devices.

as I know, the break-down voltage of the PN junction between the drain and the substrate of N3 is not higher than the break-down voltage of the gate of N2. So I think that using N3 to tolerance 5V is not reasonable.
who can tell me why I am wrong.

BTW, when the PAD is 5V, the ESD device of P1 is turned on so it is not good here. Am I right? What is the better solution for ESD?

[quote author=boris]
as I know, the break-down voltage of the PN junction between the drain and the substrate of N3 is not higher than the break-down voltage of the gate of N2.
[quote]

You are wrong in this statement. The N+/P-sub break-down in higher than 5V for sure. If I recall correccly it is 10-12V. You can check it by simulating N+/P-sub reverse-biased diode and see. (if of course you have reliable and good models from the FAB).

You are also wrong in the statement about the P1 is turning on. It is not. First, the Vt of 3.3V transistors is about 0.7V, but the voltage at the pad NEIVER reach 5V, because: second, P+/NWELL diode (which is the drain of P1) becomes forward biased and opens when the pad voltage reaches Vt of this diode (it may be 0.4-0.6V) above VDD (the voltage of the NWELL). You also can simulate P+/NWELL diode (in this case forward biased) and see when it will open (i.e. find the diode Vt).

Best,
Michael