Cadence provides a number of connect rules.. and connect models for this purpose ..
once you find the library (in the IUS5.7 installation) you can grep the files for sensitivity
on my recent projects, I've moved from the default "logic" discipline (which I know conflicts with SystemVerilog
which I may use someday) and have defined my one..
the REAL reason I do this is that I use a NON-supply sensitive discipline for my LOW voltage gates (I don't have to modify them to get them to work in AMS)
and then I use a different supply sensitive discipline for my other (High voltage) logic..
and I don't allow a connection between the two, except with a properly modeled Level shifter..
XIG12LS33 for example.. (with my ams model for it)
default "logic_cmos" is for 1.2v only
"logic_ss" is for 2.5v or "switched" supplies that I assume are not compatible with the 1.2v logic..
then I have a set for CML gates.. (see my upcoming bmas paper @
www.bmas-conf.org.. Any chance you can make it out for that?
Jonathan
Jonathan