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bernd

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Munich/Germany

How to assign supply voltage specific CRs to net
Mar 31^st, 2006, 12:34am

In Cadence AMS Designer, what's the easiest or
most straight forward way to assign supply voltage
specific connect rules to specific nets.

Assuming you have three supply voltages in the
analog and one in the digital domain,
e.g. analog 1.2V core, 1.8V IO, 3.3V IO,
digital 1.2V core.

Do I have to write custom disciplines in an
own 'disciplines.vams'?
If yes where should I put it to be recognized
by the tool?

To be honest I did not realy understand how the
process works here, if it woks at all!?

Bernd

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Just another lonesome cad guy

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Andrew Beckett

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Life, don't talk to
me about Life...

Posts: 1742
Bracknell, UK

Re: How to assign supply voltage specific C
Reply #1 - Mar 31^st, 2006, 2:40am

Bernd,

This can be done with supply sensitive connect modules - which can discover the supply of the digital block to which they are connected, using (say) inherited connections.

It's covered in the documentation, if I remember rightly... and there are examples of such connect modules in the sample connect modules provided in the IUS stream.

You could do it with custom disciplines, but that's probably more of a pain to manage - you'd have multiple discrete disciplines. I've
done this in some cases where I've had different logic types (e.g. logic), but if you have the same standard cells operating under different
supply voltages, the supply sensitive connect modules approach is the way to go.

There are other alternatives too these days, but after the initial setup, supply sensitive connect modules are probably the way I'd choose.

Regards,

Andrew.

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jbdavid

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Posts: 378
Silicon Valley

Re: How to assign supply voltage specific C
Reply #2 - Aug 5^th, 2006, 3:55am

Cadence provides a number of connect rules.. and connect models for this purpose ..
once you find the library (in the IUS5.7 installation) you can grep the files for sensitivity

on my recent projects, I've moved from the default "logic" discipline (which I know conflicts with SystemVerilog
which I may use someday) and have defined my one..
the REAL reason I do this is that I use a NON-supply sensitive discipline for my LOW voltage gates (I don't have to modify them to get them to work in AMS)
and then I use a different supply sensitive discipline for my other (High voltage) logic..
and I don't allow a connection between the two, except with a properly modeled Level shifter..
XIG12LS33 for example.. (with my ams model for it)

default "logic_cmos" is for 1.2v only
"logic_ss" is for 2.5v or "switched" supplies that I assume are not compatible with the 1.2v logic..

then I have a set for CML gates.. (see my upcoming bmas paper @www.bmas-conf.org.. Any chance you can make it out for that?
Jonathan
Jonathan

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jbdavid
Mixed Signal Design Verification

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