Hi Cri,
It's me again
.
Quote:for this reason I guess, "module" should be added in the Stop List of the Hierarchy Editor
No this is not the case, for AMS Designer netlisting works different than for all
other DFII based netlisters, just the switch view list and their order is important. I thought Andrew posted somewhat more detailed about this in this forum, but I couldn't find it.
Quote:Did anybody find a similar problem? Do you have some suggestion?
Yes I had a problem that logic cells which contain so called UDPs (User Defined Primitives), were not expanded correct by the Hierarchy Editor.
The reason for that is that for cells containing UPD's as instances
the pc.db (parent child database) of the cell view is either missing or
has a missing instance entry for the UDP, if I was informed correct.
The workaround is to put an instance name for your UPD in the verilog code,
also this should be fixed for the most recent IUS 5.7 version.
This does not work:
Code:module AND_XX (Y, A, B);
output Y;
input A, B;
U_AND (Y, A, B)
...
endmodule
This works:
Code:module AND_XX (Y, A, B);
output Y;
input A, B;
U_AND I0 (Y, A, B)
...
endmodule
Bernd