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Cri Azzolini

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Posts: 48
University of Parma, Italy

instantiation of functional blocks for AMSdesigner
Jun 06^th, 2006, 4:02am

Hi all,

I am going to simulate a circuit containing analog blocks (schematic views) and digital blocks (functional views). The functional view instantiates standard logic gates as "module"; for this reason I guess, "module" should be added in the Stop List of the Hierarchy Editor (I use the AMS plugin for Hierarchy Editor), am I correct?

Unfortunately some standard logic gates have a hierachy below: for instance each module of AND_XX logic gates are modeled with the same U_AND "module" as a template whereas information about delays and fanout are defined in the AND_XX module. Hope this is clear Wink

I have also the "module" view of these templates (U_AND) but they are not shown in the hierarchy of my design! It seems as the standard logic gates are considered the lower level of hierarchy but there are the templates below!!

Did anybody find a similar problem? Do you have some suggestion?

I am available for further explanations about this topic.
Thanks a lot,
Cri

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bernd

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Munich/Germany

Re: instantiation of functional blocks for AMSdesi
Reply #1 - Jun 6^th, 2006, 5:27am

Hi Cri,

It's me again Wink

.

Quote:

for this reason I guess, "module" should be added in the Stop List of the Hierarchy Editor

No this is not the case, for AMS Designer netlisting works different than for all
other DFII based netlisters, just the switch view list and their order is important. I thought Andrew posted somewhat more detailed about this in this forum, but I couldn't find it.

Quote:

Did anybody find a similar problem? Do you have some suggestion?

Yes I had a problem that logic cells which contain so called UDPs (User Defined Primitives), were not expanded correct by the Hierarchy Editor.

The reason for that is that for cells containing UPD's as instances
the pc.db (parent child database) of the cell view is either missing or
has a missing instance entry for the UDP, if I was informed correct.

The workaround is to put an instance name for your UPD in the verilog code,
also this should be fixed for the most recent IUS 5.7 version.

This does not work:
Code:

module AND_XX (Y, A, B);
output Y;
input A, B;

 U_AND (Y, A, B)

...
endmodule

This works:
Code:

module AND_XX (Y, A, B);
output Y;
input A, B;

 U_AND I0 (Y, A, B)

...
endmodule

Bernd

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Just another lonesome cad guy

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Cri Azzolini

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Posts: 48
University of Parma, Italy

Re: instantiation of functional blocks for AMSdesi
Reply #2 - Jun 14^th, 2006, 5:39am

Hi Bernd,

thanks a lot for your precious suggestions! Now it seems to me the environment is completely set; I have only one more question.
Whenever I change a little bit my schematic and I update the config view, the file "verilog.vams" inside the module view of the UDP logic cells (which is actually a symbolic link) is automatically erased and the subsequent "Design Prep" of AMSDesigner complains that the "verilog.vams" file of UDP modules is missing!

I solved this problem making the link as new and removing the "master.tag" file inside the UPD modules but I did not understand this behaviour.Did you make your mind about how the AMSDesigner manages the modules' files for logic gates?

Bye and thanks,
Cri

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bernd

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Munich/Germany

Re: instantiation of functional blocks for AMSdesi
Reply #3 - Jun 14^th, 2006, 6:09am

Sounds like a Bug to me.

I did not discover this behaviour, because our standard cell libraries
are write protected for the user. And because of that AMS Designer can not
delete anything inside of them.

If you do so you have to assign a tmp directory for AMS
to give the possibility to write the data somewhere.

Code:

DEFINE myStdLib   	<pathToLib>/myStdLib
ASSIGN myStdLib TMP     <pathToTmpLib>/amsTmpLib_myStdLib

Quote:

Now it seems to me the environment is completely set

Lucky guy I've still some issues Wink

, but no time to solve them.

Bernd

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Cri Azzolini

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Posts: 48
University of Parma, Italy

Re: instantiation of functional blocks for AMSdesi
Reply #4 - Jun 14^th, 2006, 7:05am

Thanks Bernd,

probably it is a bug. Actually I made a copy of our standard cell lib into my home directory to understand how it works!
The suggestion to modify the cds.lib as you proposed will surely turn out to be useful as soon as I will come back to the official standard cells in the design-kit hierarchy.

I have to say that my environment is "almost" set but I am quite optimistic!

Thanks and bye,
Cri

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jbdavid

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Posts: 378
Silicon Valley

Re: instantiation of functional blocks for AMSdesi
Reply #5 - Aug 5^th, 2006, 3:40am

My solution was just to compile (ncvlog ) the entire standard cell library .v file..
I don't use -use5x, but this way all the UDP's are in the pak file..

But thats also a temporary stop gap until I can write some perl code to add the supply pins to all the gates, along with a check if the supply voltage goes too low..
and the supply sensitive declarations for the logic pins so I can use them with multiple supplys..

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jbdavid
Mixed Signal Design Verification

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