carbonnanotube
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Hi everybody,
I'm rather new to the topic of Verilog-A modelling; thus, I'm playing ariound with some simple models in order to get a feeling for the concepts. Doing so, I encountered a (in my opinion) strange "effect": I modelled a simple circuit (R parallel C) and simulated with Cadence Spectre:
module simpleRC(A, B); electrical A, B; branch (A, B) Cap; branch (A, B) Res; parameter real R = 1e3; parameter real C = 1e-6; analog begin I(Cap) <+ ddt(V(Cap))*C; V(Res) <+ I(Res)*R; end endmodule
which works fine. Then I change the model to the following:
module simpleRC(A, B); electrical A, B; branch (A, B) RC; parameter real R = 1e3; parameter real C = 1e-6; analog begin V(RC) <+ I(RC)*R; I(RC) <+ ddt(V(RC))*C; end endmodule
which still works (!!). That is confusing for me as I expected that the RC-Branch switches to be a flow branch representing a C only (without the parallel R).
Could anybody kindly clear this up?
Regards, Oliver
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