Ok, so I've been struggling the past week or so to run a mixed signal simulation using AMS.

I've gotten through the design prep stage fine - but now in the elaboration phase I'm encountering errors.  It seems to be the veriloga instances are not being resolved.

ncelab: *W,CUNOUN: Cannot find any unit under myLib.myCell:veriloga in the design libraries.
ncelab: *E,CUCFUN: instance 'I61' of the unit 'myCell' is unresolved in 'myLib.topCell:schematic'.

Can someone please help me figure out how to resolve these corretly?  I see other cells being resolved correctly "using config 5.x rules" - but I'm not sure what these are, or how I edit them.


Also, I have tried to create AMS netlists on 'check and save' via CIW->tools->AMS->options and selecting "Perform AMS checks", "Generate AMS netlist", and "Compile generated AMS netlist".   However, after check and save I get plenty of

"Info: No valid definition view found for library: "myLib" cell: "myCell".
       The views specified in the 'amsDefinitionViews' ams.env variable are:
       "".
       Netlisting will continue without processing the definition view..."

Can someone please clearly explain whay I need to change in ams.env exactly?


Your help is greatly appreciated!

Regards,
Raftman

Thanks, I ended up fixing the unresolved instances by copying over the default ams.env file from the installation directory.

However, I am having problems with the connect modules.  I found and installed the libraries (correctly I believe), but am getting the following error and warning.

ncelab: *W,CUCMCB (../SAR_cap_array/test_adc_ahdl/schematic/verilog.vams,91|36): Resolve connect module logic2elect binding through a search of the library which has the view
of connectrules unit, connectLib.logic2elect:module is taken.
sample_out ), .vrefpcontp( vrefpcontp[11:0] ), .dout( dout[11:0] ) );
                                                        |
ncelab: *E,CUVNCM (../SAR_cap_array/test_adc_ahdl/schematic/verilog.vams,91|57): No connection module found:Need an input port of discrete discipline logic, and an output port
of continuous discipline voltage.
sample_out ), .vrefpcontp( vrefpcontp[11:0] ), .dout( dout[11:0] ) );


I am confused because the warning (top) indicates that logic2elec was found, yet the error (bottom) complains about needing a module from "discrete/logic to continuous/voltage" -> which should be logic2elec correct?

Can you describe how you setup the connectLib (compilation, directory locations, elaborator, etc).

Many thanks!

Thanks - I found the tutorial and was able to get through it.

Now my design elaborates without errors ( a few warnings

ncelab: *W,CUCMCB (../SAR_cap_array/test_adc_ahdl/schematic/verilog.vams,90|28): Resolve connect module logic2elect binding through a search of the library which h
as the view of connectrules unit, connectLib.logic2elect:module is taken.
reset ), .vpurgecontp( net470[0:11] ), .sample( sample_in ), .vpurgecontn(

)

but I think these are ok.

However, maybe not - in simulation the outputs of my functional blocks (imported verilog) do not behave correctly.  They do not show full logic levels.  I will try to isolate the problem buy any advice will be appreciated!!




BTW, is it possible to see the full netlist (after connect modules are automatically added)?