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phase-domain model of PLL in VerilogA (Read 1613 times)
semitao
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phase-domain model of PLL in VerilogA
Aug 25th, 2006, 1:08am
 
hi, everyone,
   I want to establish the phase(frequency) domain model of PLL in VerilogA. I have read the Predicting the Phase Noise of PLL-Based Frequency Synthesizers, written by Ken Kundert. I'm confused, I don't know how to simulate this phase-domain model. Then I have several questions, I need your help. The questions as follows:
1.Why we need establish the frequecny domain model? Do we simulate it just for bandwidth and stability?
2.When I simulate the phase-domain model, which signal should I input? Just for AC simulation?
3.How to simulate the closed loop and open loop?

Thanks, all
Best regards!
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Eugene
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Re: phase-domain model of PLL in VerilogA
Reply #1 - Aug 25th, 2006, 10:02am
 
1. There are several reasons why you might want to construct a phase domain model. First, the phase domain model runs transient analyses much faster. You can even include the critical nonlinearities in your phase domain model. Second, if you move the reference and VCO integrators into the PFD, Spectre linearizes your phase domain model about frequency, which unlike phase, is a true DC quantity. With a legitimate DC operating point, you can use the phase domain model to perform parametric DC analyses that map out lock range. The DC analyses run very VERY fast. Third, the phase domain model simulates loop gain and other transfer functions without using SpectreRF. Getting a SpectreRF simulation of a closed loop voltage domain model just to converge can be pretty tricky. Trying to figure out how to extract a loop gain from the SpectreRF analysis can be even trickier. Fourth, you can add random number generators to model various noise sources and then run relatively fast transient analyses to simulate nonlinear noise effects like those you might see in a frac-N synthesizer.

2.  The input AC signal depends on what you want to see. For loop gain, I would insert the AC source between the divider and PFD.

3. Usually, the open loop simulation is for loop gain. The approach I suggested in (2) does that. I'm not sure I understand your question about the closed loop but the phase domain model works well in closed loop too, as long as you can get by the DC convergence problems. I often make my VerilogA model do different things for different analyses. For DC analysis, I make all nonlinear functions monotonic. This eliminates most convergence problems. This forces the operating point to the proper region, if a legitimate operating point exists. If it does not exist, the PFD output tells you. If the magnitude of the PFD output exceeds unity, the PLL is not locked. For transient analysis, I let the nonlinear blocks saturate.
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« Last Edit: Aug 25th, 2006, 1:12pm by Eugene »  
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semitao
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Re: phase-domain model of PLL in VerilogA
Reply #2 - Aug 27th, 2006, 7:08pm
 
Thanks, Eugene,
    I have another question, why we need move the reference and VCO integrators into the PFD? If does that, is the model not same as the circuit. And when I simulate the phase-domain model in Predicting the Phase Noise of PLL-Based Frequency Synthesizers written by Ken Kundert , I found in the bode diagram the initial phase at low frequency is -90, but in my loop should be -180.

Best regards!
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Eugene
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Re: phase-domain model of PLL in VerilogA
Reply #3 - Aug 27th, 2006, 8:39pm
 
Regarding your first question, there are two reasons to move the integrators into the PFD.
1. You can refer to the documentation on the state space averaged PFD model in the "Introduction to the PLL library" section of the SpectreRF users's guide. But briefly, if you look at the duty cycle of the PFD pulses as a function of phase error, you see a sawthooth waveform. If phase runs out along the positive horizontal axis and then reverses direction, the trajectory does not retrace; the trajectory exhibits hysteresis. A static model, one that has no memory, can not capture hysteresis. The integrator gives the PFD memory. By resetting the integrator when the duty cycle hits +/-1, the integrator exactly captures the PFD's hysteretic behavior. You can also make the reset point non-zero to capture the frequency feedback mode when the frequency error is large.

2. If you leave the integrators in the VCO and reference, Spectre linearizes the model about VCO phase. To see the problem with this, think of the PLL as a motor. The shaft angle represents the phase of the VCO. If the motor is designed to operate at a fixed speed, for stability you might want to linearize your motor about speed instead of shaft angle. Shaft angle is not a true steady state quantity. Shaft speed (or VCO frequency) is.

NOTE: Moving the integrators into the PFD is still a legitimate operation for a frac-N synthesizer because the sigma delta modulator has a discrete time integration between the sd noise and the point where the noise is injected into the loop. That discrete time integrator can be approximated by a continuous time integrator which can be absorbed into the PFD along with the reference and VCO integrators.

Regarding your second question, I would have to see your schematic to make any meangful comments.
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semitao
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Re: phase-domain model of PLL in VerilogA
Reply #4 - Aug 29th, 2006, 4:41am
 
Thanks,Eugene,
     I have simulated the cadence phase-domain PLL model. But I want to use the model in Predicting the Phase Noise of PLL-Based Frequency Synthesizers. And I used laplace funtion to describe the loop filter. In this model, the signal is theta not the frequency. I used your method to simulate this model, found the open loop bandwidth is larger than close loop bandwidth. The phase of close loop is wrong. I don't know the reason.  By the way, my loop is integar frequency synthesizer, and all my block is same as Ken's.

Best Regards!
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Eugene
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Re: phase-domain model of PLL in VerilogA
Reply #5 - Aug 29th, 2006, 9:00am
 
Do you get the wrong answer with Ken's phase domain model too?

Or are you asking how to compute loop gain from a voltage domain model?

And forgive me for asking but I have to get this question out of the way: does your Laplace transfer function have the correct units? i.e. does it convert current to volts? The first time I used a Laplace model of the loop filter I forgot that the charge pump output was current and computed the transfer function from volts to volts instead of current to volts.
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semitao
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Re: phase-domain model of PLL in VerilogA
Reply #6 - Aug 29th, 2006, 6:33pm
 
V(out)<+K*laplace_nd(I(in),{1,1/Wz},{0,1,1/Wp})

This is my loop filter transfer funtion, I think it has no problem. By the way, in a voltage domain model, there is cross() statement, it seems can not do AC simulation.

Thanks.
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semitao
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Re: phase-domain model of PLL in VerilogA
Reply #7 - Aug 29th, 2006, 8:03pm
 
I have found the reason. In Ken's PFD model : I(out)<+gain*Theta(pin,nin)/(2*`PI); It should be I(out)<+-gain*Theta(pin,nin)/(2*`PI);

Thanks, Eugene
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Ken Kundert
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Re: phase-domain model of PLL in VerilogA
Reply #8 - Aug 30th, 2006, 11:22am
 
Thanks for pointing out my mistake. I have corrected it and updated the paper.

-Ken
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