Jitter in a PLL can come from a bunch of different sources, and they all need to be considered:
A partial list that I can think of off the top of my head (and some suggested fixes)
Ground noise coupling into the delay cell. (keep it differential and a current source at the bottom to isolate the delay element)
Power noise coupling into the delay cell.
(put an internal voltage regulator over the ring oscillator to keep this quiet)
Noise coupling into the VCO control line (filter inside the chip, not outside)
Noise coupling between stages of the delay cells in the VCO (layout with good attention to grounding and substrate contacts, and localized HF filtering very close to each cell)
Noise coupling between delay cells thought the VCO control line (localized filter to remove this transition path)
Imbalance of capacitive paths between delay cells. (fix the layout)
Transitioning the delay cell before it has an opportunity to settle out fully again. (Architect to allow the cell to sit stable for a while before transitioning again)
Slew rate of the delay cell transitions being a long slope (edge to edge jitter is a product of two things, noise on the signal and the slope of the signal as it transistions.)
Charge injection in the charge pump structure (use an balanced H-bridge current steering architiecture, compensation for charge injection and the follower op-amp to stransition the current steering switches to similar voltage to what goes into the charge pump.)
And the list goes on and on and on.....
I need to write a book!
Jerry