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Simulator cannot determine necessary timestep (Read 2939 times)
Pavel
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Lausanne/Switzerland
Simulator cannot determine necessary timestep
Oct 25th, 2006, 3:51am
 
Hello

Is there any option that could make the Spectre simulator "more intelligent" in timestep choice.
When I display excursion of V(out) on some seconds simulation time

parameter real FREQ = 13.56M;
parameter real AMPL = 1;

analog V(out) <+ AMPL*sin(`M_TWO_PI*FREQ*$abstime);


I see horisontal line.

Is defining the value of Maxstep in Simulator settings only choice for credible simulations.

Thanks in advance.

Pavel.
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Daniel_Platte
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Re: Simulator cannot determine necessary timestep
Reply #1 - Oct 25th, 2006, 5:07am
 
$bound_step might solve your problem "smarter" than limiting maxstep. See Verilog-AMS LRM 2.2 section 10.8 for example.

Daniel
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Pavel
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Re: Simulator cannot determine necessary timestep
Reply #2 - Oct 27th, 2006, 1:31am
 
Ok, Thanks.
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