Hi,
My circuit accepts the TTL level input, I found the PWD(pulse width distortion) degrade seriously when the input TTL level varies,because the TTL level is defined as the low is less 0.8V and the high level is larger 2V. My circuit uses 0.6um CMOS process and works in 5V supply. The PWD degradation comes from the thereshold of the input can not track the different input TTL level, it becomes worse when the edge speed of input TTL is slower.

Can anyone pls. tell me how to handle this issue?

Thanks in advance

Hi,

You have to make the edge sharp if you want to reduce the distortion or noise.


Best regards,
Yawei