Hi Ken,
Thank you very much for so much good advices.
This is a sigma-delta modulator. The opamps, switches, and all logic gates are written in Verilog-A language. They are the cells in ahdlLib or bmslib. I want to set up a testbench using those cells to reduce the simulation time at the initial stage of the design.
Part of the circuit is shown below. For example, an ideal pulse voltage source is fed to the input of a xor/xnor gate. Other pulse sources go to corresponding logic gates like NAND and NOR. One part of its verilog-A code for xor/xnor gate is listed here.
Code: @ (cross(V(vin1) - vtrans, 1)) logic1 = 1;
@ (cross(V(vin1) - vtrans, -1)) logic1 = 0;
@ (cross(V(vin2) - vtrans, 1)) logic2 = 1;
@ (cross(V(vin2) - vtrans, -1)) logic2 = 0;
I belived the cross function must affect the time step. But it obviously failed.
I tried two spectre versions. One is spectre of sub-version 7.1.1.187.isr11. The other is spectre of sub-version 5.10.41_USR6.081308.
Best Regards,
Yawei