mc66
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Posts: 6
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you know when you layout ,you can dram a perfect symmetry MOS device
but when you manufcture it,it's a diffrent story,we can't align two layer exactly as layout,there misalign between two diffrent layer,so in silicon,there is no really symmetry MOS
eg: In layout the space of cont to poly is same in both S/D,but in silicon,poly align to active,ct align to poly,and misalign exist.so there are different space of cont to poly in S/D.
the design rule for guide layout take accout how much misalign of two layer and the cd variation of each layer.
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