The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
May 11th, 2024, 2:17pm
Pages: 1
Send Topic Print
wrong noisefigure of current mixer in veriloga (Read 5866 times)
Jochen
Junior Member
**
Offline



Posts: 11
Nuremberg, Germany
wrong noisefigure of current mixer in veriloga
Dec 19th, 2006, 7:33am
 
Hello all,

I am trying to build a model of a double-balanced passive current mixer including IIP2 and Noise Figure. The implementation of the IIP2 worked but at noise simulations (qpnoise and pnoise) i got a NF 3db higher than set. The source code and setup is posted below.

When I choose maxclockorder higher than 2 I get 3.47db too much.
With pss/pnoise and referencesideband=-1 I achieve completely wrong results of about 270db noise figure.
With isource as input I get the correct pnoise_gain but no noise figure is calculated.

As output I used a port (also tried vdc) at the testif_mix pin in order to measure only lo*rf=if, so IP2 cannot be responsible for the wrong results. I am not sure if my noise simulation setup is correct, especially for current mixers.

Do you have any idea what is wrong and how I can fix it? Any help apreciated!

Thank you very much,
Jochen

p.s.: Forgot to mention that the 3 db remain even if I comment out the line with the noise source. With no additional (mixer) noise simulation should give 0db noise figure, I believe.

my simulation setup, Code:
parameters prf=-30 frf=1.9G fif=100M flo=frf-fif

PORT2 (net38 0) port r=50 num=2 dc=0 type=dc noisetemp=27
port1 (inp 0) port r=50 num=1 type=sine freq=frf dbm=prf noisetemp=27 fundname="frf"
V0 (lo 0) vsource type=pulse edgetype=halfsine val0=-1.0 val1=1.0 period=1/flo width=1/flo/2 fundname="flo"
R1 (if_ia 0) resistor r=1K isnoisy=no
R0 (if_ib 0) resistor r=1K isnoisy=no
I1 (inp 0 lo net38 if_ia if_ib) mixer iip2=30 gain_db=0 nf_db=10

simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf
qpss  qpss  funds=["flo"  "frf"]  maxharms=[4  3] errpreset=moderate  saveinit=yes  annotate=status
qpnoise  qpnoise  start=1  stop=2G  dec=1  values=[1.9G] clockmaxharm=2  oprobe=PORT2  iprobe=port1  refsideband=  
     [1  0] annotate=status

saveOptions options save=allpub currents=all useprobes=yes
 



my mixer veriloga-model, Code:
// input has to be matched for correct ip2!
`include "constants.h"
`include "disciplines.h"
module mixer(mix_rf_a, mix_rf_b, lo_in, testif_mix, mix_if_a, mix_if_b);
inout mix_rf_a, mix_rf_b, lo_in, mix_if_a, mix_if_b, testif_mix;
electrical mix_rf_a, mix_rf_b, lo_in, mix_if_a, mix_if_b, testif_mix;

parameter real rin        = 50.0;
parameter real iip2       = 10.0;
parameter real gain_db = 0;
parameter real nf_db    = 10;
real iin, iout, iif, lo, a, b, amp_iip2, gain_lin, nf_lin, noise_current_sqrd;

analog begin
  @(initial_step) begin
   //amp_iip2 = sqrt(2*rin*0.001*pow(10,iip2/10.0));   // voltage equation
   amp_iip2    = sqrt(2/rin*0.001*pow(10,iip2/10.0));     // 1/rin for current!
   gain_lin = pow(10,gain_db/20);
   nf_lin    = pow(10, nf_db/10);

   noise_current_sqrd = 4.0 *(nf_lin-1) *`P_K*$temperature /rin;
   $display("noise-current-sqrd= %g", noise_current_sqrd);
   a = gain_lin;
   b = a / amp_iip2;
 end

  //reading input
  iin = I(mix_rf_a, mix_rf_b);
  lo  = V(lo_in);
  
  //mixing
  iif  = iin * lo;          
  I(testif_mix) <+ iif;

  //applying nonlinearity,  first mix then ip2 approach
  iout = (a* `M_PI/2 -b*iif) *iif; //compensating T/2 conv-loss for correct ip2
  I(mix_if_a, mix_if_b) <+ iout;

  //Noise Current
  I(mix_rf_a) <+ white_noise(noise_current_sqrd, "mixer_noise_current");
  
  //Input resistance
  V(mix_rf_a, mix_rf_b) <+ I(mix_rf_a, mix_rf_b) * rin;
end
endmodule
 

Back to top
« Last Edit: Dec 19th, 2006, 11:48pm by Jochen »  

mixer.png
View Profile   IP Logged
Jochen
Junior Member
**
Offline



Posts: 11
Nuremberg, Germany
Re: wrong noisefigure of current mixer in veriloga
Reply #1 - Jan 12th, 2007, 6:04am
 
Meanwhile I have conducted some further considerations of my mixer:

When I choose maximum clock order of qpnoise very high (about 30) my noise figure deviation is about +3.9 db, exactly the conversion loss of the T/2-mixer!
Is it correct to select a maximum clock order higher than the harmonics setting in qpss?
I believe to have read that one should increase the max-clock-order till the noise result is not changed any more? Is that correct?

A different approach was to add an output noise-current source [with Nout = G^2 *4kT/R * (noisefactor-1)]:
With that setting I also got a NoiseFigure 3.9db too high (with DirectPlot->MainForm->Qpnoise).
But when I calculated the Noise Figure myself with data from the Results->Print->NoiseSummary I achieved the correct noise figure!
[Maths: 10*log(TotalOutputNoise/Src_Port-OutputNoise)]

I believe that Cadence considers the conversion loss of mixers through the reference-sideband-setting? Why does it then change the NoiseFigure result?
I am considering if the attenuation through the mixer (conversion loss) increases the noise figure by the same amount. Passive filters would. Could that be?
Or is it a problem of the software?

Btw. can anybody explain me how the pnoise-value (qpnoise, transfer function) is calculated, please?

I am grateful for any comments!
Thanks in advance,
Jochen
Back to top
 
 
View Profile   IP Logged
Jochen
Junior Member
**
Offline



Posts: 11
Nuremberg, Germany
Re: wrong noisefigure of current mixer in veriloga
Reply #2 - Feb 6th, 2007, 2:04am
 
Now i have learnt that these results are correct!

A noiseless mixer gives 3db SSB-NF and
the higher the max. clock order setting is the more noise is folded into the IF-band
so >3db for  m.c.o. > 1 is correct!
It has nothing to do with the conversion gain of the mixer!

Another question:
What values does the Print->NoiseSummary give? Peak- or RMS-V^2 ??

My simulated figures are not  V2out/Hz = V2port*Gain2 =4kTR *Gain2 (the only noisy device is the port @input)
I only get half the value! Is it an voltage divider beween Rport and Rin?
Or is it because of an peak-rms conversion?
But 4kTR is already a rms-value.  :-/

Thanks for your help!
Back to top
 
« Last Edit: Feb 7th, 2007, 1:56am by Jochen »  
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.