I just got through a frustrating tape out using calibre, and perhaps someone can help point me towards a fix for next time.  Here is basically what happened.  I had two cells that were LVS clean; however, when I connected the cells together at the top level I got massive errors, even though the layout connections were correct.  

The first clue: I looked at the layout netlist and it wasn't keeping the same hierarchy.  
The second clue: Some other people got around the problem by deleting lower level ports

So we can probably say the port names of lower level cells were being brought up to the top level, that is, their names weren't being properly propigated through the hierarchy.  So if the net name changed as it made its way through the hierarchy you could get an error.  Note I said "could," because you didn't always get an error.  

one of the names that changed on the way up was the power supply, but, again, this didn't produce an error every time it happened.

Any ideas?

rg