I found the following data for the minimu channel length variation in a 0.6um CMOS technology:
Min = 0.43 um Typ =0.6 um Max 0.67 um
Now if you consider the worst case you will have:
ratio mirror * 0.43/0.67 = 100 * 0.43/0.67 = 64
This variation could explain your measurements. Probably, increasing your minimu channel length will improve dramatically your current mirror ratio.
What about your technology minimum length variations?
dandelion wrote on Mar 19th, 2007, 2:37am:mg777 wrote on Mar 17th, 2007, 7:52am:1. What is the substrate bias in your measurements? How are you forcing I
in and measuring I
out - using a SMU?
2. What are the source voltages of the two top transistors?
3. Are the devices drawn 0.6 μm supposed to be min length?
4. Plot (sim & meas) Fig. 4.9(b) on p 267 of Gray, Hurst, Lewis, & Meyer (4th ed).
M.G.Rajan
www.eecalc.com Hi mg777,
Thanks for the reply.
The sub is connected to the GND.There is no sub pin in my chip.
In simulation, the source voltage have no mcuh difference and the match is good.But the test gives much descranpancy.
yes, it is the minimum length.