Andrew Beckett
Senior Fellow
Offline
Life, don't talk to me about Life...
Posts: 1742
Bracknell, UK
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This seems reasonable behaviour to me.
If you only want to use an integer for single bit operation, you can always and the results with 1:
(a~^b)&1
which will give what you're expecting.
In Verilog-AMS you can use logic signals, and so define the bit length of the word you want. But in Verilog-A, you just have integers.
Regards,
Andrew.
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