dear friends,

i have a problem in DC/DC buck. please view the attached fig.

this is output of my DC/DC. it seems that there is a DC ripple, DC is not constant, but the value of riplle is very small (1~3mv). based on my privous projects the output should be very flat.

is it stable? or unstable? or some other reason?

could you give me a hint?

best regards,

It is possible that it is the integration method. Trapezoidal integration method tends to create small oscillations in the transient response. Try changing the integration method to Gear if there is a transient analysis option to do so. If not, then tightening the tolerances a bit may help as suggested above.

It might be helpful to zoom in on the ripple. If the frequency of the ripple is the same as your switching frequency then you have some clock feedthrough which may come from device capacitances. An FFT of the output signal may make it a bit easier to see the frequency content.

Thanks everyone very much.

i have asked for my leader and the engineer of Synopsys. they give the similar answer with yours.
i process the below steps:

decrease the simulation step;
adjust the method;
increase the accurate;

the result becomes better (but the ripple is still  :( ). now i dont think it is a problem. i am waiting for the chip.