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Can you define these MOS netlists? (Read 4638 times)
hande.vinayak
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Can you define these MOS netlists?
Apr 24th, 2007, 10:36pm
 
Hi to all,
   I am having below given mos net lists, can anybody help me realize this...?,

1.What device does it interpret?
2.When can we use these?
3.What is the special in these devices which are form by MOS?

(drain gate source body)

Net lists..
1. in in in avdd pmos   (in is an input pin)
2. on on on avss nmos (on is an input pin)
3. avdd avdd avdd avdd pmos
4. avss avss avss avss nmos
5. avss reference avss avss nmos (reference is a net)

Thnx.
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krishnap
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Re: Can you define these MOS netlists?
Reply #1 - Apr 24th, 2007, 11:10pm
 
Hi Vinayak,

From the netlsit it appears that these are nmos and pmos.
usually first four keywords are for the S G D B terminal of the MOS  and
the last keyword is the MOS  type. i,.e.,Which type of model to use.(PMOS, NMOS etc.,)
And the order of terminals depends on the simulator.
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hande.vinayak
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Re: Can you define these MOS netlists?
Reply #2 - Apr 24th, 2007, 11:34pm
 
Thnx Krishna,
But my doubt is these mos forms two different caps,
what is the significance of those (reference to netlist of 1,2 & 5)?
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adesign
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Re: Can you define these MOS netlists?
Reply #3 - Apr 25th, 2007, 9:38pm
 
Vinayak,

First and second line of netlist will give high ESR cap, whereas fifth line signifies low ESR cap.
Hope it clears.

Regards,
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hande.vinayak
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Re: Can you define these MOS netlists?
Reply #4 - Apr 25th, 2007, 11:25pm
 
Thnx,
  As reference to last post,I am having one doubt..
Is it important to connect a high ESR cap at input terminal/pin?
What affect it will make on circuit operation if we connect low ESR cap to input terminal/pin?  

Thnx n Regards.
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adesign
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Re: Can you define these MOS netlists?
Reply #5 - Apr 26th, 2007, 12:30am
 
Where do you want to connect this cap? Please elaborate on the circuit architecture.
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hande.vinayak
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Re: Can you define these MOS netlists?
Reply #6 - Apr 26th, 2007, 5:40am
 
The mentioned 'in' is a one of input of charge pump for PLL.
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