Hi,

This may have been answered elsewhere within the forum but my limited understanding makes it difficult to find the answer!

How does the phase noise of the reference oscillator in a PLL map to the PLL output?

For example, in a clock distribution design the phase noise of the master reference must determine the attainable phase noise in the subsequent stages.  In terms of phase noise offsets from the reference, do these points multiply up by the divider ratio to the output, or do the offset frequencies themselves remain the same its just their level which increases by the 'N' divider ratio?

The crooks of the question is this.  If I use an oscillator as a reference to a PLL, and it outputs 2GHz say, and I use the same reference for a 3GHz PLL - does my reference oscillator need to be cleaner to achieve the same phase noise for both PLLs?

Hope I'm making sense here!

Best Regards

I would like to expand on the very last statement from MG Rajan, regarding time jitter.  

The absolute time jitter should be the same for both cases (i.e. 1psec rms at 10MHz is 1psec rms at 2GHz and 3GHz.)  But the UI will be more at 3G than at 2G, because the period at 3G is less than at 2G.  That is assuming that the PLL BW is set such that the reference jitter is the dominant jitter at the output.  For example, 1 psec rms at 2GHz = 2mUI, while 1 psec rms at 3GHz = 3mUI.