Hi,

Would anyone know how the deep n-well is connected in the layout for capacitors and MOSFETs ? Does it have to be connected to any of the supplies Vdd/Gnd ? Is it tied to the bulk ? Is it left floating ? During a DRC, I end up with a psubStampError and have a feeling it is because I've left the deep N-well floating.

I'm designing this for an RF IC.

Any help is appreciated. Thanks, in advance. Cheers.

Thanks for that, ACWWong

I am using the TSMC 0.18. The schematic doesn't seem to show any explicit connections for the d-nwell. I was of the same opinion (that I should connect it to VDD to minimise the diode cap.), but was wondering that it would complicate the layout with the additional connection to VDD. That would make an already compact layout pretty crowded !
Have you had a similar experience with TSMC 0.18, D-Nwell ?

Thanks for all your replies !