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Phase Noise and Jitter Measurements
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jitter simulation for a 16 bit ADC (Read 3069 times)
analog2000
Junior Member
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Posts: 21
jitter simulation for a 16 bit ADC
Jun 17
th
, 2007, 1:40pm
Hi,
I am designing a vco for a 16 bit ADC. Can some one tell me what frequency offsets I should use to simulate jitter for a 16 bit ADC ?
thanks
analog2000
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ywguo
Community Fellow
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Posts: 943
Shanghai, PRC
Re: jitter simulation for a 16 bit ADC
Reply #1 -
Jun 19
th
, 2007, 7:46pm
Hi,
I am not clear what is your question. What is your spec/requirement on the clock for your 16bit ADC? I don't know the reason why you simulate jitter with frequency offset.
Yawei
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jeffyan
Community Member
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Posts: 47
Re: jitter simulation for a 16 bit ADC
Reply #2 -
Jun 27
th
, 2007, 5:47pm
analog2000 wrote
on Jun 17
th
, 2007, 1:40pm:
Hi,
I am designing a vco for a 16 bit ADC. Can some one tell me what frequency offsets I should use to simulate jitter for a 16 bit ADC ?
thanks
analog2000
hi
plz have a look at these posts:
http://www.designers-guide.org/Forum/YaBB.pl?num=1166075659
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