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VCO glitches in Verilog-A (Hspice) (Read 2550 times)

imtired

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Santa Rosa

VCO glitches in Verilog-A (Hspice)
Jun 20^th, 2007, 12:08pm

Hi,

Using the VCO behavioral model from this website (with jitter), once in a while the VCO output level exceeds +/-1. Simulating within a PLL, the longer I simulate, the greater the excursion. Also, I am setting the jitter to zero, so it actually doesn't have any jitter being applied.

Has anyone previously observed such behavior? Any hints, suggestions, insight as to what might be going on, and steps to resolving it?

Any help would be appreciated.

Thanks,
Robert

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Geoffrey_Coram Senior Fellow Offline Posts: 1998 Massachusetts, USA	Re: VCO glitches in Verilog-A (Hspice) Reply #1 - Jun 21^st, 2007, 10:32am The output voltage of the vco exceeds vh?? In vco2, I see: V(out) <+ transition(n ? vh : vl, 0, tt); so it seems like it must be a simulator bug (in the transition function?) if the output voltage is ever outside the range (vl,vh), assuming vl < vh.
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