adauto6 wrote on Aug 16th, 2007, 11:08am:Do i have to put one model to do the AC analysis and other to do the DC e TRAN analysis ??
I'm not very familiar with VHDL-AMS, but I strongly discourage people from doing that sort of hackery when writing Verilog-AMS models. The simulator should do the linearization of the model for use in ac analysis, in order to ensure consistent ac and transient results.