satya wrote on Sep 18th, 2007, 12:20am:Hi,
I come across a spec of 6ps rms jitter for a pll.
what actually this refers to? and feasible?
is this random jitter?
generally the jitter what we calculate from phase noise is what jitter type?
please give ur comments
I would recommend you explore the genesis of the requirement. I believe you need a bit more information to properly break the requirement down to requirements for the individual components of your phase-locked loop. Typically, a standard drives the jitter generation requirement for a phase-locked loop. Most all standards (expect SONET/SDH) break the jitter down ino a requirement for both random and deterministic jitter components. Specific questions that I would try to resolve are:
1. The bandwidth over which the 6 ps rms jitter requirement is measured
2. The manner in which the 6 ps rms jitter is to be measured (this provides insight into the type of jitter to which the requirement is referring)
3. If a data recovery based phase-locked loop (i.e., a CDR), the data pattern applied to the input during which the jitter is measured
4. If a data recovery based phase-locked loop (or if the clock is used to retime data) , the bit error rate over which the jitter requirement exists
As for a 6 ps jitter being feasible, many phase locked loops are capable of providing a 6 ps rms random output jitter component for jitter measurement bandwidths of 10 kHz and greater. The issue of course, is highly dependent on the jitter of the reference clock to the PLL, the bandwidth and jitter transfer of the PLL and the internal VCO noise of the PLL. Hence, there is not a "general" answer.
Finally, phase noise data contains both random and determistic jitter. One must take efforts to examine the random and deterministic components when computing the jitter through the use of bandwidth limiting, applying specific data patterns and jitter decomposition.
Hope this helps,
Shawn
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6ps rms jitter spec (Read 4314 times)