I'm not sure if this is the right forum, but here goes:  MOSIS has pages like this one (http://www.mosis.com/cgi-bin/cgiwrap/umosis/swp/params/tsmc-018/t77a_mm_non_epi_...) for the process they work with, and there is a section containing ring oscillator power and frequency measurements.   Does anyone know what test structure they use to come up with these numbers?  When I try to duplicate the measurements in simulation with a ring oscillator of minimum-sized inverters (Wn=Wmin; Wp=2*Wmin), I come up with about 4x less power and about 40% higher frequency than they do.  

The lines I'm talking about look like this:
 DIV1024 (31-stg,1.8V)                 0.02  uW/MHz/gate
which made me think maybe DIV1024 is a standard structure, but I haven't been able to find anything on it.

Thanks,
Jeremy

I think this is the divide by 10 structure where input clock is devided by 1024 after 10 stages.