I like to use 1.5x min width and space, and double vias.  If you set up some test cases, I think you'll find that this gives a nice improvement of the RC characteristic of the wire without too much area expense.  The dual-damascene metalization structure results an a resistivity penalty at minimum width beyond linear ohms/square.  You're generally not worried about substrate capacitance for interconnect, rather area and sidewall capacitances to other traces.  Since sidewall is greater than area at minimum pitch, the  1.5xmin-width/space provides a net reduction in capacitance even though the area-cap has increased.

Current density is of concern on highly loaded nets.  You mention clock trunks.  If possible, put these on top-level thick metal.  You'll find explicit current density rules in your process documentation.  AC rules are much easier to satisfy than DC.  In fact  current-density violations are the industry's dirtly little secret at the moment.

I'll add the comment that the bulk of CMOS is routed at minimum pitch.  So it's definitely reasonable to expect decent results with that configuration.