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modeling sdm using verilog-A (Read 5196 times)
min
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modeling sdm using verilog-A
Jan 08th, 2008, 9:36pm
 
Hi :
I have being modeling a 2nd DT sdm using verilog-A. I have model the diff-ota with verilog-A, and I use ideal switch in analogLib.
the diff-ota verilog-A model ac and tran simulation result is right.
but when I put these model in sdm , the simulator accuracy setting is conservative , when simulation the simulator will have convergence error, and I could't get the result.
when I change the simulator accuracy setting to moderate, the simulator will have no error, and I will get the result. but the result has more harmonics.
Is my diff-ota modeling has problem , or  modeling the switch cap filter has some special requirement to the ota verilog a modeling?

Min
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sheldon
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Re: modeling sdm using verilog-A
Reply #1 - Jan 9th, 2008, 4:49am
 
Min,

  I have built second-order Sigma-Delta Modulators using Verilog-A. One suggestion
you might want to try is using the switch model in bmslib, sw_no. The transfer function
is smooth and continuous and has very good convergence. using it should allow you
to use the more accurate error preset.

                                                                       Best Regards,

                                                                         Sheldon
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Ken Kundert
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Re: modeling sdm using verilog-A
Reply #2 - Jan 9th, 2008, 11:04am
 
Do you need to model the switch as a separate entity? I have had great success combining the amplifiers and switches into one behavioral model.

-Ken
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