joel
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In practice, I've repeatedly found that cascaded-pll systems work better if the 2nd pll has a higher loop bandwidth. In my situation, both plls are roots of clock-domains, and data needs to be moved from the first pll's clock-domain to the 2nd. So the 2nd pll needs to track the 1st pll's 'medium-term' jitter. I think if you're not moving data from the 1st pll's clock domain to the 2nd pll's clock domain, you could get lower jitter by lowering the 2nd pll's loop-bandwidth.
I ended up having to add a circuit that detected excessive misalignment between the 1st and 2nd pll's clocks, which could result in loss of synchronous data transfer between the domains. This would then generate an interrupt, warning the system of data loss. Alternatively, you could put in fifos, at the expense of area & complexity.
You would do well to put some loop-bandwith tuning parameters under register control. Like doubling both the M, N, or adjusting the charge-pump current (if its a charge-pump pll). Just some system thoughts for you. Good luck!
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