In practice, I've repeatedly found that  cascaded-pll systems work better if the 2nd pll has a higher loop
bandwidth.  In my situation, both plls are roots of clock-domains, and data needs to be moved from
the first pll's clock-domain to the 2nd.  So the 2nd pll needs to track the 1st pll's  'medium-term' jitter.
I think if you're not moving data from the 1st pll's clock domain to the 2nd pll's clock domain, you could
get lower jitter by lowering the 2nd pll's loop-bandwidth.

I ended up having to add a circuit that detected excessive misalignment between the 1st and 2nd pll's clocks,
which could result in loss of synchronous data transfer between the domains.  This would then generate an interrupt,
warning the system of data loss.  Alternatively, you could put in fifos, at the expense of area & complexity.

You would do well to put some loop-bandwith tuning parameters under register control.  Like doubling both the M, N,
or adjusting the charge-pump current (if its a charge-pump pll). Just some system thoughts for you.  Good luck!

I just meant this:
 
 pll1 produces a clock1 that clocks a  register-bank-1 (RB1)
 pll2 produces a clock2 that clocks a register-bank-2 (RB2)

 @(posedge clock2) if (enable==1) RB2 = RB1;

So clock1 and clock2 must be plesiochronous, love that word!  CDR is a different story.
I've never cascaded 5 plls, but I'd worry about the stages where you've got a 1MHz-bandwidth
pll driving a 40KHz-bandwidth pll.  In this case, the clock from the 1MHz-bandwidth PLL might
be able to jitter quite far from the 40KHz-bandwidth pll's output clock.  After all, the 40KHz-bandwidth
pll is set up to reject high-frequency phase noise on its input clock.

I hope someone smart pitches in with some theory to analyze this, and maybe a strategy for simulation.

Hi nowicq,

Why NOT a DLL to generate 8 phases, then select one? I don't understand why you need 5 cascade PLL's.

If you cascade 5 PLL's, the jitter accumulates more and more, especially in the loop bandwidth.


Best regards,
Yawei