AnalogDE
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Hi,
I'm designing a high speed, unity-gain amplifier. It has a settling time of 15ns, driving a capacitive load of 60pF. I'm using a current mirror OTA architecture, with NMOS inputs. Common mode range is 0.9V to 1.35V with a minimum supply VDD of 1.6V (eek). Nominal gain is 40ish dB, which drops to 30 dB with the 1.35V input and VDD=1.6V (current mirror approaching linear region).
Could somebody suggest an architecture (rail-to-rail?) that does not lose as much gain when the inputs approach the rails?
Thanks!
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