The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Feb 20th, 2020, 1:49pm
Pages: 1
Send Topic Print
Chip on board parasitical model (Read 5812 times)
email_gz
Junior Member
**
Offline



Posts: 31
gaoz.mail@gmail.com
Chip on board parasitical model
Mar 30th, 2008, 7:06pm
 
Does any one know the COB parasitical model?
How about the normal value per mm of Rp, Cp ,Lp, Mp/Kp?
Thank you very much:)
Back to top
 
 
View Profile email_gz email_gz   IP Logged
pancho_hideboo
Senior Fellow
******
Offline



Posts: 1424
Real Homeless
Re: Chip on board parasitical model
Reply #1 - Mar 31st, 2008, 8:31am
 
email_gz wrote on Mar 30th, 2008, 7:06pm:
Does any one know the COB parasitical model?
How about the normal value per mm of Rp, Cp ,Lp, Mp/Kp?
Thank you very much:)

What do you mean by COB ?
Is it discreate chip components ?

Back to top
 
 
View Profile WWW Top+Secret Top+Secret   IP Logged
email_gz
Junior Member
**
Offline



Posts: 31
gaoz.mail@gmail.com
Re: Chip on board parasitical model
Reply #2 - Apr 2nd, 2008, 1:07am
 
pancho_hideboo wrote on Mar 31st, 2008, 8:31am:
email_gz wrote on Mar 30th, 2008, 7:06pm:
Does any one know the COB parasitical model?
How about the normal value per mm of Rp, Cp ,Lp, Mp/Kp?
Thank you very much:)

What do you mean by COB ?
Is it discreate chip components ?


Hello:
    COB means Chip on board, just bonding the die to PCB .
Back to top
 
 
View Profile email_gz email_gz   IP Logged
pancho_hideboo
Senior Fellow
******
Offline



Posts: 1424
Real Homeless
Re: Chip on board parasitical model
Reply #3 - Apr 6th, 2008, 11:05pm
 
In ADS, there are bondwire models. These are available also in RFDE.

See Chapter 4: Passive RF Circuit Components of the followings.

http://eesof.tm.agilent.com/docs/adsdoc2005A/pdf/ccdist.pdf

BONDW_Shape (Philips/TU Delft Bondwire Parameterized Shape)
BONDW_Usershape (Philips/TU Delft Bondwire Model with User-DefinedShape)
BONDW1 to BONDW50 (Philips/TU Delft Bondwires Model)
Back to top
 
 
View Profile WWW Top+Secret Top+Secret   IP Logged
email_gz
Junior Member
**
Offline



Posts: 31
gaoz.mail@gmail.com
Re: Chip on board parasitical model
Reply #4 - Apr 14th, 2008, 8:47pm
 
Thank you pancho_hideboo,it should be helpful to me!
Back to top
 
 
View Profile email_gz email_gz   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2020 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.