Hi,
I am deisgning an block which is PECl output. I found my process provide an NPN Tr and so I intend to use it to implement the PECL level. The NPN Tr is N+/P/NWELL topology. The base is located in the NWELL.

I communicated with the foundr, they said although this device is availble, it is not tested ever, so they can not guarantee if it have any risks. They said the beta of this device is 20 or so.

Would you pls. give any advice in using this device? Any risks ? What about its permance in mass production?

Thanks

Risks would be: if the device completely fails to act as a transistor, the foundry will still make you pay for the wafers because it's not a supported device.

You might want to have a look at the masks that make it up and how they might go bad.  Eg, what happens if the N+ implant goes too deep and shorts out the NPN: will this also cause a supported device to fail?  In this case, I think you wouldn't have to pay for the wafers.