Hi, all
In a delta sigma DAC, classical implementation is Digital interpolator -->Digital DSM -->Switch Cap dac & Filter --> active filter . Now, i want to replace the Switch Cap dac with current steering dac to save area and power consumption. The question is coming, how to resolve the jiter problem? The dac level is just 9.
All comments are welcome.

hi,Yawei
   Thanks for your reply. Switch cap implementation is a discrete time style, the final settled value is of most concern. But in a current steering DAC circuit, the full time value must be cared, the jitter will introduce the error in transform process, just in a Continuous time Sigma Delta ADC which is a hot topic in mixed signal ic design nowadays, if the feedback dac is a current steering form, the jitter will normally restrict the whole system performance. Expect more discussion.
   san.