caosl_zju
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Posts: 22
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hi,Yawei Thanks for your reply. Switch cap implementation is a discrete time style, the final settled value is of most concern. But in a current steering DAC circuit, the full time value must be cared, the jitter will introduce the error in transform process, just in a Continuous time Sigma Delta ADC which is a hot topic in mixed signal ic design nowadays, if the feedback dac is a current steering form, the jitter will normally restrict the whole system performance. Expect more discussion. san.
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