While the modelling of very narrow and long devices may not be quite accurate, I would be surprised if a 2/10 device is not modelled correctly. The W is not really minimum there. I assume you are not using a 2 um technology The aspect ratio is also not so bad.

If you want to get a good idea about the W, L values for which you have a good model, just look at your process doc. Usually, there are some notes about the transistor dimensions used in model parameter extraction. This is done for several different sizes, and the results are interpolated to arbitrary size devices.

Did you simulate your circuit across all reasonable corners and with the realistic input voltages?

Regards
Vivek

Theory #2 is that the latch inverter uses two transistors close to minimum size in the forward path and very long in the feedback path. So although this circuit simulates fine, on siicon, the two minimum transistors would be very susceptible to process variation and may be much weaker than expected (so the feedback inverter is overloading the output net).

Since the circuit is in the corner of the die, perhaps these very small transistors are badly registered.