I was running the Verilog-A logic gates from:
http://www.designers-guide.org/VerilogAMS/functional-blocks/gates/gates.vain a commercial simulator, and I got this warning:
VERILOG-A PERFORMANCE WARNING:
"gates.va", line 125: The first argument to the transition filter is a
continuous signal, which might slow down the simulation.
Further occurrences of this warning will be suppressed.
If I change, for example,
V(out) <+ transition( !((V(in1) > vth) && (V(in2) > vth)) ? vh : vl, td, tt );
to
vout = ( !((V(in1) > vth) && (V(in2) > vth))) ? vh : vl;
V(out) <+ transition( vout, td, tt );
then I don't get the warning, and the simulation runs 40x faster!