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Anyone have experience with IBM CMOS design kit? (Read 3313 times)
tkhan
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Anyone have experience with IBM CMOS design kit?
Sep 17th, 2008, 11:56am
 
Hi,

I have an instance of symmetric inductor and it has the option of adding a center tap. Regardless of whether there is a CT or not, the spectre view still has the 3rd terminal. When I simulate a circuit using this inductor, I get the same results with or without the CT enabled (keeping all other parameters equal). When I look at the layout pcell, there is clearly a difference between the CT and no CT layouts (i.e. the presence of the CT). When I plot the voltage on the net connected to the CT, it is the same with and without the CT enabled. Any insight? Thanks.
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RFsage
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Re: Anyone have experience with IBM CMOS design kit?
Reply #1 - Sep 18th, 2008, 12:58am
 
Hi,

Which inductor model are you using? (symind or symindp) and what is the width of center tap connection you are using? According to the model the center tap resistance is modeled as "rct" resistance. Check the value of rct in both cases of simulation.

Hope this helps.

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bernd
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Re: Anyone have experience with IBM CMOS design kit?
Reply #2 - Sep 18th, 2008, 1:26am
 
Have you debugged your simulators netlist if there is a difference if you using the CT and no CT option?
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tkhan
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Re: Anyone have experience with IBM CMOS design kit?
Reply #3 - Sep 20th, 2008, 3:14pm
 
Thanks for the replies. I am using symindp_inh model (there is no symind in my kit).

I looked into netlist, without the CT the model has the following parameters:

I12 (I\- I\+ net19 0) symindp x=300.0000u s=5u w=3u wu=-1u n=13 tlev1=3 \
       tlev2=2 bp=8 dtemp=0

With the CT the model has the following parameters:

I12 (I\- I\+ net19 0) symindp x=300.0000u s=5u w=8.5u wu=9.24u n=9 tlev1=3 \
       tlev2=2 bp=8 dtemp=0

(net19 is between D of current source PMOS and CT).

The width of the CT is the minimum parameterized value, 8.5μm. It seems there is no rct in the netlist, i will look into the model file to see the differences.
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