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vivkr

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reverse leakage current of diodes in CMOS processes
Oct 22^nd, 2008, 11:36pm

Hi,

I was wondering how well-controlled the reverse leakage currents of standard p-n junctions are. Let's assume a good analog process, and p-n junctions which are part of the active device such as source/drain diffusions to well/substrate, and junctions which are part of a BJT, and its interface to the substrate.

Basically, these diodes are always modelled because they are part of the active devices, and the parameters of the active devices are well-controlled in general within the process limits. So, if I am told that the MOS and BJT parameters are always guaranteed to be within the simulated range, can I also assume that the diode leakage will also always be as I see in simulations? I mean the diode leakage is a fairly simple (compared to other things) function of the doping and structure.

Or is it at all possible that the MOS device or BJT functions can be preserved within min/max limits and the diode leakage still be excessively high (excepting process defects)? It seems illogical to me but I am unable to get any definite answer from the foundry. Is this also dependent on the foundry? We are assuming that the MOS is modelled for analog design in all cases.

Could someone comment on this?

Thanks,
Vivek

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Tlaloc

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Dallas, TX

Re: reverse leakage current of diodes in CMOS processes
Reply #1 - Oct 31^st, 2008, 2:26pm

For my part, I've been taught to not trust the absolute accuracy of the models in the leakage regime. I don't know if there was an issue with how our modeling teams were modeling the devices or if there was an issue with the bsim model itself. Newer models may be more accurate.

By the way, it seems like you would also be interested in the channel leakage as well as junction leakage, especially as the channel leakages are so dominant at the small geometries.

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Maks

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Re: reverse leakage current of diodes in CMOS processes
Reply #2 - Nov 1^st, 2008, 8:26pm

Reverse leakage in p-n junctions depends not only on fundamental (well-known, or process-controlled) factors (such as doping profile, electric field, etc.), but also on "chemical" factors, such as presence of contaminants (e.g., metallic impurities), defects, stress, etc. These factors are not that well controlled in standard logic or analog processes. Fabs and foundries are trying to make silicon as "clean" as possible, within given constraints (e.g. financial). In some technologies, such image sensor, DRAM, other memory (T-RAM, Z-RAM,...), reverse junction leakage is the ultimate factor, determining dark current (low light noise), retention time, etc., and fabs are doing everything possible to reduce the leakage, and to increase carrier lifetime (roughly speaking, leakage is inversely proportional to carrier generation lifetime).

"Standard" device characteristics (Vt, Idsat, Gm,...) are practically insensitive to lifetime, so foundries may not be paying much attention or monitoring it. Even though reverse p-n junction leakage may be specified by compact device models, the accuracy and reliability of these models may is questionable, in my opinion.

Maks

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Geoffrey_Coram

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Re: reverse leakage current of diodes in CMOS processes
Reply #3 - Nov 3^rd, 2008, 5:40am

Tlaloc wrote on Oct 31^st, 2008, 2:26pm:

For my part, I've been taught to not trust the absolute accuracy of the models in the leakage regime. I don't know if there was an issue with how our modeling teams were modeling the devices or if there was an issue with the bsim model itself. Newer models may be more accurate.

The JUNCAP2 model, which is part of the PSP mosfet model, includes several leakage equations: SRH recombination, trap-assisted tunneling, and band-to-band tunneling. BSIM3 just has one diode equation; BSIM4 does add TAT. I don't know how hard it is to separate these effects or to what extent they scale differently with W and L (and other layout geometries, like nearby well edges); they do likely scale differently with temperature.

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weggy New Member Offline Posts: 2	Re: reverse leakage current of diodes in CMOS processes Reply #4 - Dec 17^th, 2008, 10:51pm Geoffrey_Coram/ Could you explain how to use JUNCAP2? I'm also looking for way to estimate BTBT leakages. Is there a library with 45nm tech for JUNCAP2?
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Geoffrey_Coram

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Re: reverse leakage current of diodes in CMOS processes
Reply #5 - Dec 18^th, 2008, 6:08am

I think with any of these models, you have to have measured data in order to determine the parameters that go into the equations. It's not something you can compute directly from process data. Eg, for trap-assisted tunneling, you can't measure the trap density in your silicon nor estimate it from the ID/VD curves; you have to specifically measure the diode leakage current across temperature, bias, geometry, and then try to figure out how much of the current is TAT and how much BBT.

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weggy New Member Offline Posts: 2	Re: reverse leakage current of diodes in CMOS processes Reply #6 - Dec 18^th, 2008, 7:24am Thanks for your quick reply. :) Do you know the level 54 BSIM4 have BBT cosideration in the library? I found they have GIDL in cosideration but I don't know about BBT.
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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: reverse leakage current of diodes in CMOS processes Reply #7 - Dec 19^th, 2008, 5:44am I may have misspoken; BSIM4 seems to have trap-assisted tunneling (NJTS* parameters), but not band to band.
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