Maks
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Posts: 52
San Jose
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Reverse leakage in p-n junctions depends not only on fundamental (well-known, or process-controlled) factors (such as doping profile, electric field, etc.), but also on "chemical" factors, such as presence of contaminants (e.g., metallic impurities), defects, stress, etc. These factors are not that well controlled in standard logic or analog processes. Fabs and foundries are trying to make silicon as "clean" as possible, within given constraints (e.g. financial). In some technologies, such image sensor, DRAM, other memory (T-RAM, Z-RAM,...), reverse junction leakage is the ultimate factor, determining dark current (low light noise), retention time, etc., and fabs are doing everything possible to reduce the leakage, and to increase carrier lifetime (roughly speaking, leakage is inversely proportional to carrier generation lifetime).
"Standard" device characteristics (Vt, Idsat, Gm,...) are practically insensitive to lifetime, so foundries may not be paying much attention or monitoring it. Even though reverse p-n junction leakage may be specified by compact device models, the accuracy and reliability of these models may is questionable, in my opinion.
Maks
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